View M58LW128BZA_1270097.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M58LW128A M58LW128B
128 Mbit (8Mb x16 or 4Mb x32, Uniform Block, Burst) 3V Supply Flash Memories
PRELIMINARY DATA
FEATURES SUMMARY s WIDE DATA BUS for HIGH BANDWIDTH - M58LW128A: x16 - M58LW128B: x16/x32
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Figure 1. Packages
SUPPLY VOLTAGE - VDD = 2.7 to 3.6V core supply voltage for Program, Erase and Read operations - VDDQ = 1.8 to VDD for I/O Buffers
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SYNCHRONOUS/ASYNCHRONOUS READ - Synchronous Burst read - Pipelined Synchronous Burst Read - Asynchronous Random Read - Asynchronous Address Latch Controlled Read - Page Read
TSOP56 (N) 14 x 20mm
TBGA
TBGA64 (ZA) 10 x 13mm
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ACCESS TIME - Synchronous Burst Read up to 66MHz - Asynchronous Page Mode Read 150/25ns - Random Read 150ns
TBGA
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PROGRAMMING TIME - 16 Word or 8 Double-Word Write Buffer - 12s Word effective programming time
TBGA80 (ZA) 10 x 13mm
s s s s s s
128 UNIFORM 64 KWord MEMORY BLOCKS BLOCK PROTECTION/ UNPROTECTION PROGRAM and ERASE SUSPEND OTP SECURITY AREA COMMON FLASH INTERFACE 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE - Manufacturer Code: 0020h - Device Code M58LW128A: 8818h - Device Code M58LW128B: 8819h
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February 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M58LW128A, M58LW128B
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. TBGA64 Connections for M58LW128A (Top view through package) . . . . . . . . . . . . . . . 9 Figure 5. TBGA80 Connections for M58LW128B (Top view through package) . . . . . . . . . . . . . . 10 Figure 6. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A1-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Burst Address Advance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Word Organization (WORD).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program/Erase Enable (VPP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input/Output Supply Voltage (VDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ground (VSSQ ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Asynchronous Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Synchronous Pipelined Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3. Synchronous Burst Read Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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M58LW128A, M58LW128B
Table 4. Address Latch Cycle for Optimum Pipelined Synchronous Burst Read . . . . . . . . . . . . . Figure 7. Synchronous Burst Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 8. Example Synchronous Pipelined Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . Figure 9. Example Burst Address Advance and Burst Abort operations . . . . . . . . . . . . . . . . . . . . 17 18 18 19
Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 X-Latency Bits (M14-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Y-Latency Bit (M9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Latch Enable Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. Burst Type Definition (x16 Bus Width). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 7. Burst Type Definition (x32 Bus Width). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 8. Burst Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Block Protect Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . 28 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VPP Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 12. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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M58LW128A, M58LW128B
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 14. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 10. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 15. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 16. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 12. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 17. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 13. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 36 Table 18. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . 36 Figure 14. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 19. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 15. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 38 Figure 16. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled . . . . . . 38 Table 20. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 17. Asynchronous Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . 40 Figure 18. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 40 Table 21. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 19. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 20. Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . 43 Table 22. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 21. Reset, Power-Down and Power-Up AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 23. Reset, Power-Down and Power-Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 45 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . Table 24. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data Figure 23. TBGA64 - 10x13mm - 8 x 8 ball array, 1mm pitch, Package Outline . . . . . . . . . . . . . . Table 25. TBGA64 - 10x13mm - 8 x 8 ball array, 1 mm pitch, Package Mechanical Data . . . . . . Figure 24. TBGA80 - 10x13mm - 8 x 10 ball array, 1mm pitch, Package Outline . . . . . . . . . . . . . Table 26. TBGA80 - 10x13mm - 8 x 10 ball array, 1mm pitch, Package Mechanical Data. . . . . . 46 46 47 47 48 48
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 28. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 29. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4/65
M58LW128A, M58LW128B
Table 30. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 31. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 32. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 33. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 34. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 54 55 55 56
APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 25. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . Figure 26. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . Figure 27. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . Figure 29. Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . Figure 30. Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . Figure 31. Command Interface and Program Erase Controller Flowchart (c) . . . . . . . . . . . . . . . . 57 58 59 60 61 62 63
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 35. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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M58LW128A, M58LW128B
SUMMARY DESCRIPTION M58LW128 is a 128 Mbit (8Mb x16 or 4Mb x32) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7V to 3.6V) core supply. On power-up the memory defaults to Read mode with an asynchronous bus where it can be read in the same way as a non-burst Flash memory. The memory is divided into 128 blocks of 1Mbit that can be erased independently so it is possible to preserve valid data while old data is erased. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The Write Buffer allows the microprocessor to program up to 16 Words (or 8 Double Words) in parallel, both speeding up the programming and freeing up the microprocessor to perform other work. The minimum buffer size for a program operation is an 8 Word (or 4 Double Word) page. A page can only be programmed once between Erase operations. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. Individual block protection against program or erase is provided for data security. All blocks are protected during power-up. The protection of the blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state when power was last removed. Software commands are provided to allow protection of some or all of the blocks and to cancel all block protection bits simultaneously. All program or erase operations are blocked when the Program Erase Enable input Vpp is low. The Reset/Power-Down pin is used to apply a Hardware Reset to the memory and to set the device in Power-Down mode. It can also be used to temporarily disable the protection mechanism. In asynchronous mode Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. An Address Latch input can be used to latch addresses in Latch Controlled mode. Together they allow simple, yet powerful, connection to most microprocessors, often without additional logic. In synchronous mode all Bus Read operations are synchronous with the Clock. Chip Enable and Output Enable select the Bus Read operation; the address is Latched using the Latch Enable inputs and the address is advanced using Burst Address Advance. The signals are compatible with most microprocessor burst interfaces. A One Time Programmable (OTP) area is included for security purposes. Either 512 Words (x16 Bus Width) or 512 Double-Words (x32 Bus Width) is available in the OTP area. The process of reading from and writing to the OTP area is not published for security purposes; contact STMicroelectronics for details on how to use the OTP area. The memory is offered in various packages. The M58LW128A is available in TSOP56 (14 x 20 mm) and TBGA64 (1mm pitch). The M58LW128B is available in TBGA80 (1mm pitch).
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M58LW128A, M58LW128B
Figure 2. Logic Diagram Table 1. Signal Names
A1 Address Input (x16 Bus Width only) Address inputs Data Inputs/Outputs Data Inputs/Outputs (x32 Bus Width of M58LW128B only) Burst Address Advance Chip Enable Output Enable Clock Latch Enable Valid Data Ready Ready/Busy Reset/Power-Down Program/Erase Enable Write Enable Word Organization (M58LW128B only) Supply Voltage Input/Output Supply Voltage Ground Input/Output Ground Not Connected Internally A2-A23 DQ0-DQ15
VDD VDDQ 23 A1-A23 VPP W E G RP L B M58LW128A M58LW128B 16 DQ16-DQ31 RB R
(1)
16 DQ0-DQ15
DQ16-DQ31 B E G K L R RB RP VPP
K WORD
(1)
W WORD VDD
VSS VSSQ
AI04314
VDDQ VSS VSSQ NC
Note: 1. M58LW128B only.
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M58LW128A, M58LW128B
Figure 3. TSOP56 Connections
A22 R A21 A20 A19 A18 A17 A16 VDD A15 A14 A13 A12 E VPP RP A11 A10 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1 1 56 NC W G RB DQ15 DQ7 DQ14 DQ6 VSSQ DQ13 DQ5 DQ12 DQ4 VDDQ VSS DQ11 DQ3 DQ10 DQ2 VDD DQ9 DQ1 DQ8 DQ0 B K A23 L
AI04315
14 43 M58LW128A 15 42
28
29
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M58LW128A, M58LW128B
Figure 4. TBGA64 Connections for M58LW128A (Top view through package)
1
2
3
4
5
6
7
8
A
A1
A6
A8
VPP
A13
VDD
A18
A22
B
A2
VSS
A9
E
A14
NC
A19
R
C
A3
A7
A10
A12
A15
NC
A20
A21
D
A4
A5
A11
RP
NC
NC
A16
A17
E
DQ8
DQ1
DQ9
DQ3
DQ4
NC
DQ15
RB
F
K
DQ0
DQ10
DQ11
DQ12
NC
NC
G
G
A23
B
DQ2
VDDQ
DQ5
DQ6
DQ14
W
H
L
NC
VDD
VSS
DQ13
VSSQ
DQ7
NC
AI04316
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M58LW128A, M58LW128B
Figure 5. TBGA80 Connections for M58LW128B (Top view through package)
1 2 3 4 5 6 7 8
A
A1
A8
VSS
E
A13
VDD
A18
A22
B
A2
A7
A9
A12
A14
A16
A19
R
C
A3
A6
A10
VPP
A15
A17
A20
A21
D
A4
A5
A11
RP
A23
NC
NC
NC
E
DQ16
DQ25
DQ19
WORD
DQ6
DQ28
DQ22
DQ31
F
DQ24
DQ18
DQ27
DQ10
DQ13
DQ20
DQ29
DQ23
G
DQ17
DQ26
L
DQ3
DQ5
W
DQ21
DQ30
H
K
B
DQ2
DQ11
DQ12
DQ15
RB
G
J
DQ0
DQ1
VDD
VSS
DQ4
VSSQ
VSSQ
DQ7
K
DQ8
DQ9
VDD
VSS
VDDQ
VDDQ
VDDQ
DQ14
AI04318
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M58LW128A, M58LW128B
Figure 6. Block Addresses
M58LW128A, M58LW128B Word (x16) Bus Width Address lines A1-A23 7FFFFFh 7F0000h 7EFFFFh 7E0000h M58LW128B Double-Word (x32) Bus Width Address lines A2-A23 (A1 is Don't Care) 3FFFFFh 3F8000h 3F7FFFh 3F0000h Total of 128 1 Mbit Blocks 1 Mbit or 32 KDouble-Words 1 Mbit or 32 KDouble-Words
1 Mbit or 64 KWords 1 Mbit or 64 KWords
01FFFFh 010000h 00FFFFh 000000h
1 Mbit or 64 KWords 1 Mbit or 64 KWords
00FFFFh 008000h 007FFFh 000000h
1 Mbit or 32 KDouble-Words 1 Mbit or 32 KDouble-Words
AI06130
Note: Also see Appendix A, Table 28 for a full listing of the Block Addresses
SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A1-A23). The Address Inputs are used to select the cells to access in the memory array during Bus Read operations either to read or to program data to. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Chip Enable must be low when selecting the addresses. The address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a write operation. The address latch is transparent when Latch Enable is low, V IL. The address is internally latched in a program or erase operation. With a x32 Bus Width, WORD = VIH, Address Input A1 is ignored; the Least Significant Word is output on DQ0-DQ15 and the Most Significant Word is output on DQ16-DQ31. With a x16 Bus Width, WORD = VIL, the Least Significant Word is output on DQ0-DQ15 when A1 is low, V IL, and the Most Significant Word is output on DQ0-DQ15 when A1 is high, V IH. Data Inputs/Outputs (DQ0-DQ31). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation, or are used
to input the data during a Program operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. When used to input data or write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. When Chip Enable and Output Enable are both low, V IL, the data bus outputs data from the memory array, the Electronic Signature, the Block Protection status, the CFI Information or the contents of the Status Register. The data bus is high impedance when the chip is deselected, Output Enable is High, VIH, or the Reset/Power-Down signal is Low, VIL. When the Program/Erase Controller is active the Ready/Busy status is given on DQ7 while DQ0-DQ6 and DQ8-DQ31 are high impedance. With a x16 Bus Width, WORD = VIL, DQ16-DQ31 are not used and are high impedance. Chip Enable (E). The Chip Enable, E, input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power consumption to the Standby level, IDD1. Output Enable (G). The Output Enable, G, gates the outputs through the data output buffers during a read operation. When Output Enable, G, is at VIH
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M58LW128A, M58LW128B
the outputs are high impedance. Output Enable, G, can be used to inhibit the data output during a burst read operation. Write Enable (W). The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data can be latched on the rising edge of Write Enable (also see Latch Enable, L). Reset/Power-Down (RP). The Reset/PowerDown pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected. A Hardware Reset is achieved by holding Reset/ Power-Down Low, VIL, for at least tPLPH. When Reset/Power-Down is Low, VIL, the Status Register information is cleared and the current is reduced to IDD2 (refer to Table 16, DC Characteristics). The device is deselected and outputs are high impedance. If Reset/PowerDown goes low, VIL,during a Block Erase, a Write to Buffer and Program or a Block Protect/Unprotect the operation is aborted and the data may be corrupted. In this case the Ready/Busy pin stays low, V IL, for a maximum timing of tPLPH + tPHRH. After Reset/Power-Down goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tRHEL. Note that Ready/Busy does not fall during a reset, see Ready/Busy Output section. During power-up Reset/Power-Down must be held Low, V IL. Furthermore it must stay low for tVDHPH after the Supply Voltage inputs become stable. The device will then be configured in Asynchronous Random Read mode. See Table 23 and Figure 21, Reset, Power-Down and Power-up Characteristics, for more details. Holding RP at VHH will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. In an application, it is recommended to associate Reset/Power-Down pin, RP, with the reset signal of the microprocessor. Otherwise, if a reset operation occurs while the memory is performing a program or erase operation, the memory may output the Status Register information instead of being initialized to the default Asynchronous Random Read. Latch Enable (L). The Bus Interface can be configured to latch the Address Inputs on the rising edge of Latch Enable, L. In synchronous bus operations the address is latched on the active edge of the Clock when Latch Enable is Low, V IL. Once latched, the addresses may change without affecting the address used by the memory. When Latch Enable is Low, VIL, the latch is transparent. Clock (K). The Clock, K, is used to synchronize the memory with the external bus during Synchro12/65
nous Bus Read operations. The Clock can be configured to have an active rising or falling edge. Bus signals are latched on the active edge of the Clock during synchronous bus operations. In Synchronous Burst Read mode the address is latched on the first active clock edge when Latch Enable is low, VIL, or on the rising edge of Latch Enable, whichever occurs first. During Asynchronous Bus operations the Clock is not used. Burst Address Advance (B). The Burst Address Advance, B, controls the advancing of the address by the internal address counter during synchronous bus operations. Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the X- or Ylatency time has expired. If Burst Address Advance is Low, VIL, the internal address counter advances. If Burst Address Advance is High, VIH, the internal address counter does not change; the same data remains on the Data Inputs/Outputs and Burst Address Advance is not sampled until the Y-latency expires. The Burst Address Advance, B, may be tied to VIL. Valid Data Ready (R). The Valid Data Ready output, R, is an open drain output that can be used to identify if the memory is ready to output data or not. The Valid Data Ready output is only active during Synchronous Burst Read operations when the Burst Length is set to Continuous. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready Low, V OL, indicates that the data is not, or will not be valid. Valid Data Ready in a high-impedance state indicates that valid data is or will be available. Unless the Burst Length is set to Continuous and Synchronous Burst Read has been selected, Valid Data Ready is high-impedance. It may be tied to other components with the same Valid Data Ready signal to create a unique System Ready signal. When the system clock frequency is between 33MHz and 50MHz and the Y latency is set to 2, values of B sampled on odd clock cycles, starting from the first read are not considered. Designers should use an external pull-up resistor of the correct value to meet the external timing requirements for Valid Data Ready rising. Refer to Figure 20. Word Organization (WORD). The Word Organization input, WORD, selects the x16 or x32 Bus Width on the M58LW128B. The Word Organization input is not available on the M58LW128A. When WORD is Low, VIL, Word-wide x16 Bus Width is selected; data is read and written to DQ0DQ15; DQ16-DQ31 are at high impedance and A1
M58LW128A, M58LW128B
is the LSB of the address bus. When WORD is High, VIH, the Double-Word wide x32 Bus Width is selected and the data is read and written to on DQ0-DQ31; A2 is the LSB of the address bus and A1 is don't care. Ready/Busy (RB). The Ready/Busy output, RB, is an open-drain output that can be used to identify if the Program/Erase Controller is currently active. When Ready/Busy is high impedance, the memory is ready for any read, program or erase operation. Ready/Busy is Low, VOL, during program and erase operations. When the device is busy it will not accept any additional Program or Erase commands except Program/Erase Suspend. When the Program/Erase Controller is idle, or suspended, Ready Busy can float High through a pull-up resistor. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Ready/Busy is not Low during a reset unless the reset was applied when the Program/Erase Controller was active; Ready/Busy can rise before Reset/Power-Down rises. Program/ Program/Erase Enable (V PP). The Erase Enable input, VPP, is used to protect all blocks, preventing Program and Erase operations from affecting their data. When Program/Erase Enable is Low, VIL, any program or erase operation sent to the Command Interface will cause the VPP Status bit (bit3) in the Status Register to be set. When Program/Erase Enable is High, V IH, program and erase operations can be performed on unprotected blocks. Program/Erase Enable must be kept High during all Program, Erase, Block Protect and Block Unprotect operations, otherwise the operation is not guaranteed to succeed and data may become corrupt. VDD Supply Voltage. The Supply Voltage, VDD, is the core power supply. All internal circuits draw their current from the V DD pin, including the Program/Erase Controller. A 0.1F capacitor should be connected between the Supply Voltage, VDD, and the Ground, VSS, to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during all operations of the parts, see Table 16, DC Characteristics, for maximum current supply requirements. Input/Output Supply Voltage (V DDQ). The Input/Output Supply Voltage, V DDQ, is the input/output buffer power supply. All input and output pins and voltage references are powered and measured relative to the Input/Output Supply Voltage pin, V DDQ. The Input/Output Supply Voltage, VDDQ, must always be equal or less than the VDD Supply Voltage, including during Power-Up. A 0.1F capacitor should be connected between the Input/Output Supply Voltage, VDDQ, and the Ground, V SSQ, to decouple the current surges from the power supply. If VDDQ and VDD are connected together then only one decoupling capacitor is required. Ground (V SS). Ground, VSS, is the reference for all core power supply voltages. Ground (V SSQ). Ground, VSSQ, is the reference for input/output voltage measurements. It is essential to connect VSS and VSSQ to the same ground.
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M58LW128A, M58LW128B
BUS OPERATIONS The bus operations that control the memory are described in this section, see Tables 2 and 3, Bus Operations, for a summary. The bus operation is selected through the Burst Configuration Register; the bits in this register are described at the end of this section. On Power-up or after a Hardware Reset the memory defaults to Asynchronous Bus Read and Asynchronous Bus Write, no other bus operation can be performed until the Burst Control Register has been configured. Synchronous Read operations and Latch Controlled Bus Read operations can only be used to read the memory array. The Electronic Signature, CFI or Status Register will be read in asynchronous mode regardless of the Burst Control Register settings. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Asynchronous Bus Operations For asynchronous bus operations refer to Table 3 together with the text below. Asynchronous Bus Read. Asynchronous Bus Read operations read from the memory cells, or specific registers (Electronic Signature, Status Register, CFI and Block Protection Status) in the Command Interface. A valid bus operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 12, Asynchronous Bus Read AC Waveforms, and Table 17, Asynchronous Bus Read AC Characteristics, for details of when the output becomes valid. Asynchronous Latch Controlled Bus Read. Asynchronous Latch Controlled Bus Read operations read from the memory cells. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. A valid bus operation involves setting the desired address on the Address Inputs, setting Chip Enable and Address Latch Low, V IL and keeping Write Enable High, VIH; the address is latched on the rising edge of Address Latch. Once latched, the Address Inputs can change. Set Output Enable Low, VIL, to read the data on the Data Inputs/ Outputs; see Figure 13, Asynchronous Latch Controlled Bus Read AC Waveforms and Table 18, Asynchronous Latch Controlled Bus Read AC Characteristics for details on when the output becomes valid.
Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus Read operations can be performed when the memory is configured for Asynchronous Latch Enable bus operations by holding Latch Enable Low, VIL throughout the bus operation. Asynchronous Page Read. Asynchronous Page Read operations are used to read from several addresses within the same memory page. Each memory page is 8 Words or 4 Double-Words and has the same A4-A23, only A1, A2 and A3 may change. Valid bus operations are the same as Asynchronous Bus Read operations but with different timings. The first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. If the page changes then the normal, longer timings apply again. See Figure 14, Asynchronous Page Read AC Waveforms and Table 19, Asynchronous Page Read AC Characteristics for details on when the outputs become valid. Asynchronous Bus Write. Asynchronous Bus Write operations write to the Command Interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don't care during Bus Write operations. A valid Asynchronous Bus Write operation begins by setting the desired address on the Address Inputs and setting Latch Enable Low, VIL. The Address Inputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Asynchronous Bus Write operation. See Figures 15, and 17, Asynchronous Write AC Waveforms, and Tables 20 and 21, Asynchronous Write and Latch Controlled Write AC Characteristics, for details of the timing requirements. Asynchronous Latch Controlled Bus Write. Asynchronous Latch Controlled Bus Write operations write to the Command Interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don't care during Bus Write operations. A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired address on the Address Inputs and pulsing Latch Enable Low, VIL. The Address Inputs are latched by the Command Interface on the rising edge of Latch Enable, Chip Enable or Write Enable, whichever occurs
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M58LW128A, M58LW128B
first. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V IH, during the whole Asynchronous Bus Write operation. See Figures 16 and 18 Asynchronous Latch Controlled Write AC Waveforms, and Tables 20 and 21, Asynchronous Write and Latch Controlled Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when the Output Enable is High. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data InTable 2. Asynchronous Bus Operations
Bus Operation Asynchronous Bus Read Asynchronous Latch Controlled Bus Read Asynchronous Page Read Asynchronous Bus Write Asynchronous Latch Controlled Bus Write Output Disable Standby Power-Down Address Latch Address Latch Read Step E VIL VIL VIL VIL VIL VIL VIL VIH X G VIL VIL VIL VIL VIH VIH VIH X X W VIH VIH VIH VIH VIL VIL VIH X X RP High High High High High High High High VIL M3(2) 0 1 1 0 X X X X X L X VIL VIH X VIL VIL X X X A1-A23 Address Address X Address Address Address X X X DQ0-DQ31 Data Output High Z Data Output Data Output Data Input Data Input High Z High Z High Z
puts/Outputs pins are placed in the high impedance state regardless of Output Enable or Write Enable. The Supply Current is reduced to the Standby Supply Current, IDD1. During Program or Erase operations the memory will continue to use the Program/Erase Supply Current, IDD3, for Program or Erase operations until the operation completes. Power-Down. The memory is in Power-Down mode when Reset/Power-Down, RP, is Low. The current is reduced to IDD2, and the outputs are high impedance, independent of Chip Enable, Output Enable or Write Enable.
Note: 1. X = Don't Care VIL or VIH . High = VIH or VHH. 2. M15 = 1, Bits M15 and M3 are in the Burst Configuration Register.
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M58LW128A, M58LW128B
Synchronous Bus Operations For synchronous bus operations refer to Table 3 together with the text below. Synchronous Burst Read. Synchronous Burst Read operations are used to read from the memory at specific times synchronized to an external reference clock. The burst type, length and latency can be configured. The different configurations for Synchronous Burst Read operations are described in the Burst Configuration Register section. A valid Synchronous Burst Read operation begins when the address is set on the Address Inputs, Write Enable is High, VIH, and Chip Enable and Latch Enable are Low, V IL, during the active edge of the Clock. The address is latched on the first active clock edge when Latch Enable is low, or on the rising edge of Latch Enable, whichever occurs first. The data becomes available for output after the X-latency specified in the Burst Control Register has expired. The output buffers are activated by setting Output Enable Low, V IL. See Figure 7 for an example of a Synchronous Burst Read operation. The Burst Address Advance input and the Y-latency specified in the Burst Control Register determine whether the internal address counter is advanced on the active edge of the Clock. When the internal address counter is advanced the Data Inputs/Outputs change to output the value for the next address. In Continuous Burst mode (Burst Length Bit M2M0 is set to `111'), one Burst Read operation can access the entire memory sequentially and wrap at the last address. The Burst Address Advance, B, must be kept low, VIL, for the appropriate number of clock cycles. If Burst Address Advance, B, is pulled High, VIH, the Burst Read will be suspended. In Continuous Burst Mode, if the starting address is not associated with a page (4 Word or 2 Double Word) boundary the Valid Data Ready, R, output goes Low, V IL, to indicate that the data will not be ready in time and additional wait-states are required. The Valid Data Ready output timing (bit M8) can be changed in the Burst Configuration Register. When using the x32 Bus Width certain X-latencies are not valid and must not be used; see Table 5, Burst Configuration Register. The Synchronous Burst Read timing diagrams and AC Characteristics are described in the AC and DC Parameters section. See Figures 19, 20 and Table 22. Synchronous Pipelined Burst Read. Synchronous Burst Read operations can be overlapped to avoid or reduce the X-latency. Pipelined operations should only be used with Burst Configuration Register bit M9 = 0 (Y-latency setting). A valid Synchronous Pipelined Burst Read operation occurs during a Synchronous Burst Read operation when the new address is set on the Address Inputs and a Low pulse is applied to Latch Enable. The data for the new address becomes valid after the X-latency specified in the Burst Configuration Register has expired. For optimum operation the address should be latched on the correct clock cycle. Table 4 gives the clock cycle for each valid X- and Y-latency setting. Only these settings are valid, other settings must not be used. There is always one Y-Latency period where the data is not valid. If the address is latched later than the clock cycle specified in Tables 4 then additional cycles where the data is not valid are inserted. See Figure 8 for an example of a Synchronous Pipelined Burst Read operation. Here the X-latency is 8, the Y-latency is 1 and the burst length is 4; the first address is latched on cycle 1 while the next address is latched on cycle 6, as shown in Table 4. Synchronous Pipelined Burst Read operations should only be performed on Burst Lengths of 4 or 8 with a x16 Bus Width or a Burst Length of 4 with a x32 Bus Width. Suspending a Pipelined Synchronous Burst Read operation is not recommended. Synchronous Burst Read Suspend. During a Synchronous Burst Read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. A valid Synchronous Burst Read operation is suspended when both Output Enable and Burst Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops the burst counter and the Output Enable going High, V IH, inhibits the data outputs. The Synchronous Burst Read operation can be resumed by setting Output Enable Low. See Figure 7 for an example of a Synchronous Burst Read Suspend operation.
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M58LW128A, M58LW128B
Table 3. Synchronous Burst Read Bus Operations
Bus Operation Step Address Latch Read (no address advance) Read (with address advance) Synchronous Burst Read Pipelined Synchronous Burst Read Read Suspend Read Resume (no address advance) Read Resume (with address advance) Read Abort E VIL VIL VIL VIL VIL VIL VIH G X VIL VIL VIH VIL VIL X RP VIH VIH VIH VIH VIH VIH VIH K(3) T T T X T T X L VIL X X X X X X B X VIH VIL VIH VIH VIL X A1-A23 DQ0-DQ31 Address Input Data Output Data Output High Z Data Output Data Output High Z
Note: 1. X = Don't Care, VIL or VIH. 2. M15 = 0, Bit M15 is in the Burst Configuration Register. 3. T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.
Table 4. Address Latch Cycle for Optimum Pipelined Synchronous Burst Read
Address Latch Clock Cycle X-Latency 8 9 12 13 15 Y-Latency Burst Length = 4 1 1 1 1 2 6 7 10 11 11 Burst Length = 8 10 11 14 15 19
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M58LW128A, M58LW128B
Figure 7. Synchronous Burst Read Operation
0 K
1
X-1
X
X+1
Address Inputs L
Q1
B Data Inputs/ Outputs
tBLKH
tBHKH tBHKH
tBHKH
Q1
Q2
Q3
Q4
Q5
Q5
Q5
Q6
Q7
Q7
Q8
Q8
AI03454b
Note: In this example the Burst Configuration Register is set with M2-M0 = 001 (Burst Length = 4 Words or Double Words), M6 = 1 (Valid Clock Edge = Rising Clock Edge), M7 = 0 or 1 (Burst Type = Interleaved or Sequential), M9 = 0 (Y-Latency = 1), M14-M11 = 0011 (XLatency = 8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don't care.
Figure 8. Example Synchronous Pipelined Burst Read Operation
0 K Address Inputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Q1
R1
S1
L
E
G
B
Data Inputs/ Outputs
Q1
Q2
Q3
Q4
NV
R1
R2
R3
R4
NV
S1
S2
S3
NV= Not Valid
AI03455
Note: In this example the Burst Configuration Register is set with M2-M0 = 001 (Burst Length = 4 Words or Double Words), M6 = 1 (Valid Clock Edge = Rising Clock Edge), M7 = 0 or 1 (Burst Type = Interleaved or Sequential), M9 = 0 (Y-Latency = 1), M14-M11 = 0011 (XLatency = 8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don't care.
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M58LW128A, M58LW128B
Figure 9. Example Burst Address Advance and Burst Abort operations
0 K
1
X-2
X
X+2
X+4
X+6
X+8
X+10
X+12
Address Inputs L
Q1
B Data Inputs/ Outputs
tBLKH tBHKH
tBHKH
tBHKH
Q1
Q2
Q3
Q3
Q4
Q4
Q4
AI03457b
Note: 1. In this example the Burst Configuration Register is set with M2-M0 = 010 (Burst Length = 8 Words), M6 = 1 (Valid Clock Edge = Rising Clock Edge), M7 = 0 or 1 (Burst Type = Interleaved or Sequential), M9 = 1 (Y-Latency = 2), M14-M11 = 0011 (X-Latency = 8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don't care. 2. When the system clock frequency is between 33MHz and 50MHz and the Y latency is set to 2, values of B sampled on odd clock cycles, starting from the first read are not considered.
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M58LW128A, M58LW128B
Burst Configuration Register The Burst Configuration Register is used to configure the type of bus access that the memory will perform. The Burst Configuration Register is set through the Command Interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Power-Down mode. The Burst Configuration Register bits are described in Table 5. They specify the selection of the burst length, burst type, burst X and Y latencies and the Read operation. Read Select Bit (M15). The Read Select bit, M15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to '1', Bus Read operations are asynchronous; when the Read Select but is set to '0', Bus Read operations are synchronous. On reset or power-up the Read Select bit is set to'1' for asynchronous accesses. X-Latency Bits (M14-M11). The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 5, Burst Configuration Register. The X-Latency bits should also be selected in conjunction with Table 8, Burst Performance to ensure valid settings. Y-Latency Bit (M9). The Y-Latency bit is used during Synchronous Bus Read operations to set the number of clock cycles between consecutive reads. The Y-Latency value depends on both the X-Latency value and the setting in M9. When the Y-Latency is 1 the data changes each clock cycle; when the Y-Latency is 2 the data changes every second clock cycle. See Table 5, Burst Configuration Register and Table 8, Burst Performance, for valid combinations of the Y-Latency, the X-Latency and the Clock frequency. Valid Data Ready Bit (M8). The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is '0' the Valid Data Ready output pin is driven Low for the active clock edge when invalid data is output on the bus. When the Valid Data Ready bit is '1' the Valid Data Ready output pin is driven Low one clock cycle prior to invalid data being output on the bus. Burst Type Bit (M7). The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is '0' the memory outputs from interleaved addresses; when the Burst Type bit is '1' the memory outputs from sequential addresses. See Tables 6 and 7, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode. Valid Clock Edge Bit (M6). The Valid Clock Edge bit, M6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is '0' the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is '1' the rising edge of the Clock is active. Latch Enable Bit (M3). The Latch Enable bit is used to select between Asynchronous Random Read and Asynchronous Latch Enable Controlled Read. When the Latch Enable bit is set to `0' Random read is selected; when it is set to `1' Latch Enable Controlled Read is selected. To enable these Asynchronous Read configurations M15 must be set to `1'. Burst Length Bit (M2-M0). The Burst Length bits set the maximum number of Words or DoubleWords that can be output during a Synchronous Burst Read operation before the address wraps. Table 5, Burst Configuration Register gives the valid combinations of the Burst Length bits that the memory accepts; Tables 6 and 7, Burst Type Definition, give the sequence of addresses output from a given starting address for each length. M10, M5 and M4 are reserved for future use.
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Table 5. Burst Configuration Register
Address Mnemonic Bit 17 M15 Bit Name Read Select Reset Value 1 1 0010 0011 0100 0101 16 to 13 0110 1001 1010 1011 1101 Asynchronous Bus Read X-Latency = 7, use only with Continuous Burst Length X-Latency = 8 X-Latency = 9 X-Latency = 10, use only with Continuous Burst Length X-Latency = 11, use only with Continuous Burst Length X-Latency = 12 X-Latency = 13 X-Latency = 13, use only with Continuous Burst Length X-Latency = 15 x16 or x32 x16 or x32 x16 or x32 x16 or x32 x16 only x16 only x16 only x16 only x16 or x32 x16 or x32 Value 0 Description Synchronous Burst Read Valid Bus Width x16 or x32
M14-M11
X-Latency
XXXX
Others Reserved, Do Not Use. 0 11 M9 Y-Latency X 1 0 X 1 0 9 M7 Burst Type Valid Clock Edge Latch Enable X 1 0 X 1 0 0 1 100 101 4 to 2 M2-M0 Burst Length 001 XXX 010 111 8 Words Continuous x16 only x16 or x32 Latch Enable Controlled Read 1 Word or Double-Word 2 Words or Double-Words 4 Words or Double-Words x16 or x32 x16 or x32 x16 or x32 x16 or x32 Rising Clock edge Random Read x16 or x32 x16 or x32 8 M6 Sequential Falling Clock edge x16 or x32 x16 or x32 R valid Low one cycle before valid Clock edge Interleaved x16 or x32 x16 or x32 When X-Latency < 13, Y-Latency = 1 When M14-M11 = 1011 or 1101, Y-Latency = 2 When X-Latency 15 but M14-M111011 or 1101, Y-Latency = 2, When M14-M11=1011 or 1101 DO NOT USE. R valid Low during valid Clock edge x16 or x32
x16 or x32 x16 or x32
10
M8
Valid Data Ready
5
M3
Others Reserved, Do Not Use.
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M58LW128A, M58LW128B
Table 6. Burst Type Definition (x16 Bus Width)
Burst Length Starting Address (binary) A3 A2 A1 XX0 2 XX1 X00 X01 4 X10 X11 000 001 010 011 8 100 101 110 111 Continuous
Note: X = 0 or 1.
Sequential (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 A, A+1, A+2...
Interleaved (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Not Valid
A
Table 7. Burst Type Definition (x32 Bus Width)
Burst Length Starting Address (binary) A3 A2 X0 2 X1 00 01 4 10 11 8 Continuous
Note: X = 0 or 1.
Sequential (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Not Valid
Interleaved (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
A
A, A+1, A+2...
Not Valid
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Table 8. Burst Performance
X-Latency 7 8 9 x16, x32 7 8 9 10 continuous only 11 1 12 continuous, length 13 x16 only 10 11 2 12 continuous, length 13 13 2(M9=0) 15 x16, x32 66 MHz continuous only continuous, length 50 MHz continuous only 2 continuous, length 1 continuous, length 33 MHz continuous only Y-Latency Bus Width Clock Frequency Mode continuous only
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M58LW128A, M58LW128B
COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. The Commands are summarized in Table 9, Commands. Refer to Table 9 in conjunction with the text descriptions below. After Power-Up or a Reset operation the memory enters Read mode. Synchronous Read operations and Latch Controlled Bus Read operations can only be used to read the memory array. The Electronic Signature, CFI or Status Register will be read in Asynchronous mode regardless of the Burst Control Register settings. Once the memory returns to Read Memory Array mode the bus will resume the setting in the Burst Configuration Register automatically. Read Memory Array Command. The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array. While the Program/Erase Controller is executing a Program, Erase, Block Protect or Blocks Unprotect operation the memory will not accept the Read Memory Array command until the operation completes. Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code, the Device Code or the Block Protection Status until another command is issued; see Table 10, Read Electronic Signature. Read Query Command. The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Tables 29, 30, 31, 32, 33 and 34 for details on the information contained in the Common Flash Interface (CFI) memory area. Note that the addresses for the Common Flash Interface Memory Area are A1-A23 for the M58LW128A and A2-A23 for the M58LW128B, regardless of the Bus Width selected. Read Status Register Command. The Read Status Register command is used to read the Status
Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. The Status Register information is present on the output data bus (DQ1-DQ7) when both Chip Enable and Output Enable are low, V IL. See the section on the Status Register and Table 12 for details on the definitions of the Status Register bits Clear Status Register Command. The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One Bus Write is required to issue the Clear Status Register command. The bits in the Status Register are sticky and do not automatically return to `0' when a new Write to Buffer and Program, Erase, Block Protect or Block Unprotect command is issued. If any error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command. Block Erase Command. The Block Erase command can be used to erase a block. It sets all of the bits in the block to `1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Erase times are given in Table 11. See Appendix C, Figure 27, Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Write to Buffer and Program Command. The Write to Buffer and Program command is used to program the memory array. Up to 2 pages of 8 Words (or 4 Double Words) can be loaded into the Write Buffer and programmed into the memory. The 2 pages are selected by address A4. Each Write Buffer has the same A5 -A23 addresses.
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Four successive steps are required to issue the command. 1. One Bus Write operation is required to set up the Write to Buffer and Program Command. Issue the set up command with the selected memory Block Address where the program operation should occur (any address in the block where the values will be programmed can be used). Any Bus Read operations will start to output the Status Register after the 1st cycle. 2. Use one Bus Write operation to write the same block address along with the value N on the Data Inputs/Output, where N+1 is the number of Words (x16 Bus Width) or Double Words (x32 Bus Width) to be programmed. 3. Use N+1 Bus Write operations to load the address and data for each Word or Double Word into the Write Buffer. See the constraints on the address combinations listed below. The addresses must have the same A5-A23. 4. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the operation without affecting the data in the memory array. The Status Register should be cleared before re-issuing the command. The minimum buffer size for a program operation is an 8 Word (or 4 Double Word) page. Inside the page the 8 Words are selected by addresses A3, A2 and A1. For any page, only one Write to Buffer and Program Command can be issued inside a previously erased block. Any further Program operations on that page must be preceded by an Erase operation on the respective block. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. The block must be unprotected using the Blocks Unprotect command or by using the Blocks Temporary Unprotect feature of the Reset/ Power-Down pin, RP. See Appendix C, Figure 25, Write to Buffer and Program Flowchart and Pseudo Code, for a suggested flowchart on using the Write to Buffer and Program command. Program/Erase Suspend Command. The Program/Erase Suspend command is used to pause a Write to Buffer and Program or Erase operation. The command will only be accepted during a Program or an Erase operation. It can be issued at any time during an Erase operation but will only be accepted during a Write to Buffer and Program command if the Program/Erase Controller is running. One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/ Erase Controller has paused. After the Program/ Erase Controller has paused, the memory will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/ Erase Controller pausing it is possible for the operation to complete. Once the Program/Erase Controller Status bit (bit 7) indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit (bit 2) or the Erase Suspend Status bit (bit 6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 11. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Erase then the Write to Buffer and Program, and the Program Suspend commands will also be accepted. When a program operation is completed inside a Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. See Appendix C, Figure 26, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 28, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. Once the command is issued subsequent Bus Read operations read the Status Register. Set Burst Configuration Register Command. The Set Burst Configuration Register command is used to write a new value to the Burst Configuration Control Register which defines the burst length, type, X and Y latencies, Synchronous/
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Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Burst Configuration Register command. Once the command is issued the memory returns to Read mode as if a Read Memory Array command had been issued. The value for the Burst Configuration Register is always presented on A2-A17, regardless of the bus width that is selected. M0 is on A2, M1 on A3, etc.; the other address bits are ignored. Block Protect Command. The Block Protect command is used to protect a block and prevent Program or Erase operations from changing the data in it. Two Bus Write cycles are required to issue the Block Protect command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Protect operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 11. The Block Protection bits are non-volatile, once set they remain set through Reset and PowerDown/Power-Up. They are cleared by a Blocks Unprotect command or temporary disabled by raising the Reset/Power-Down pin to V HH and holding it at that level throughout a Block Erase or Write to Buffer and Program command. Blocks Unprotect Command. The Blocks Unprotect command is used to unprotect all of the blocks. Two Bus Write cycles are required to issue the Blocks Unprotect command; the second Bus Write cycle starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Unprotect operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 11.
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M58LW128A, M58LW128B
Table 9. Commands
Command Read Memory Array Read Electronic Signature Read Query Read Status Register Clear Status Register Block Erase Write to Buffer and Program Program/Erase Suspend Program/Erase Resume Set Burst Configuration Register Block Protect Blocks Unprotect Cycles Bus Write Operations 1st Addr X X X X X X BA X X BCR BA X Data FFh 90h 98h 70h 50h 20h E8h B0h D0h 60h 60h 60h BCR BA X 03h 01h D0h BA BA D0h N PA PD X D0h Addr 2nd Data Subsequent Addr Data Final Addr Data
1 1 1 1 1 2 4+N 1 1 2 2 2
Note: X Don't Care; PA Program Address; PD Program Data; BA Any address in the Block; N+1 Number of Addresses to Program; BCR Burst Configuration Register value.
Table 10. Read Electronic Signature
Code Manufacturer Code x32 x16 Device Code x32 x16 Block Protection Status x32
Note: 1. 2. 3. 4. SBA is the Start Base Address of each block. DQ31-DQ16 are available in the M58LW128B only. x32 Bus Width is available in the M58LW128B only. The address is presented on A22-A2 in x32 mode, and on A22-A1 in x16 mode.
Bus Width(3) x16
Address(4) 0020h 000000h
Data (DQ31-DQ0)(2)
00000020h 8818h (M58LW128A) 8819h (M58LW128B) 00008819h (M58LW128B) 0000h (Block Unprotected) 0001h (Block Protected) 00000000h (Block Unprotected) 00000001h (Block Protected)
000001h
SBA(1) +02h
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Table 11. Program, Erase Times and Program Erase Endurance Cycles
M58LW128A/B Parameters Min Block (1Mb) Erase Block Program Program Write Buffer Program Suspend Latency Time Erase Suspend Latency Time Block Protect Time Blocks Unprotect Time Program/Erase Cycles (per Block) Data Retention
Note: (TA = 0 to 70C; VDD = 2.7V to 3.6V; VDDQ =1.8V)
Typ 0.75 0.8 192 3 10 192 0.75
Typical after 100k W/E Cycles 0.75 0.8 192
Unit Max 5 s s s 10 30 s s s s cycles years
100,000 20
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STATUS REGISTER The Status Register provides information on the current or previous Program, Erase, Block Protect or Blocks Unprotect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Blocks Unprotect and Program/Erase Resume commands. The Status Register can be read from any address. The Status Register can only be read using Asynchronous Bus Read operations. Once the memory returns to Read Memory Array mode the bus will resume the setting in the Burst Configuration Register automatically. The contents of the Status Register can be updated during an Erase or Program operation by toggling the Output Enable pin or by dis-activating (Chip Enable, VIH) and then reactivating (Chip Enable and Output Enable, V IL) the device. During a Program, Block Erase, Block Protect or Block Unprotect operation only bit 7 is valid, all other bits are high impedance. Once the operation is complete bit 7 is High and all other Status register bits are valid. Status Register bits 5, 4, 3 and 1 are associated with various error conditions and can only be reset with the Clear Status Register command. The Status Register bits are summarized in Table 12, Status Register Bits. Refer to Table 12 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low, VOL, the Program/Erase Controller is active and all other Status Register bits are High Impedance; when the bit is High, VOH, the Program/ Erase Controller is inactive. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, Block Protect and Blocks Unprotect operations the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status and Block Protection Status bits should be tested for errors.
Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that an Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is Low, V OL, the Program/Erase Controller is active or has completed its operation; when the bit is High, VOH, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive). When the Erase Status bit is Low, V OL, the memory has successfully verified that the block has erased correctly or all blocks have been unprotected successfully. When the Erase Status bit is High, VOH, the erase operation has failed. Depending on the cause of the failure other Status Register bits may also be set to High, VOH. s If only the Erase Status bit (bit 5) is set High, VOH, then the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully. s If the failure is due to an erase or blocks unprotect with VPP low, VOL, then VPP Status bit (bit 3) is also set High, VOH. s If the failure is due to an erase on a protected block then Block Protection Status bit (bit 1) is also set High, VOH. s If the failure is due to a program or erase incorrect command sequence then Program Status bit (bit 4) is also set High, VOH. Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4). The Program Status bit is used to identify a Program or Block Protect failure. The Program Status bit should be read once
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M58LW128A, M58LW128B
the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is Low, V OL, the memory has successfully verified that the Write Buffer has programmed correctly or the block is protected. When the Program Status bit is High, VOH, the program or block protect operation has failed. Depending on the cause of the failure other Status Register bits may also be set to High, VOH. s If only the Program Status bit (bit 4) is set High, VOH, then the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the Write Buffer has programmed correctly or that the Block is protected. s If the failure is due to a program or block protect with VPP low, VOL , then VPP Status bit (bit 3) is also set High, VOH. s If the failure is due to a program on a protected block then Block Protection Status bit (bit 1) is also set High, VOH. s If the failure is due to a program or erase incorrect command sequence then Erase Status bit (bit 5) is also set High, VOH. Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. VPP Status (Bit 3). The VPP Status bit can be used to identify if a Program, Erase, Block Protection or Block Unprotection operation has been attempted when V PP is Low, VIL. The VPP pin is only sampled at the beginning of a Program or Erase operation. When the V PP Status bit is Low, VOL, no Program, Erase, Block Protection or Block Unprotection operations have been attempted with VPP Low, VIL, since the last Clear Status Register command, or hardware reset. When the VPP Status bit is High, VOH, a Program, Erase, Block Protection or Block Unprotection operation has been attempted with VPP Low, VIL. Once set High, the V PP Status bit can only be reset by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program, Erase, Block Protection or Block Unprotection command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is Low, VOL, the Program/Erase Controller is active or has completed its operation; when the bit is High, VOH, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is Low, V OL, no Program or Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is High, VOH, a Program (Program Status bit 4 set High) or Erase (Erase Status bit 5 set High) operation has been attempted on a protected block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value should be masked.
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M58LW128A, M58LW128B
Table 12. Status Register Bits
Operation Program/Erase Controller Active Write Buffer not ready Write Buffer ready Program suspended Program/Block Protect completed successfully Program/Block Protect failure due to incorrect command sequence Program/Block Protect failure due to VPP Error Program failure due to Block Protection Program/Block Protect failure due cell failure or unerased cell Erase suspended Erase/Blocks Unprotect completed successfully Erase/Blocks Unprotect failure due to incorrect command sequence Erase/Block Unprotect failure due to VPP Error Erase failure due to Block Protection Erase/Blocks Unprotect failure due to failed cell(s) in block Bit 7 Bit 6 `0' `0' `1' `1' `1' '1' '1' `1' `1' `1' `1' `1' '1' `1' `1' X(1) X(1) X(1) X(1) X(1) X(1) X(1) `1' `0' X `0' `0' `0' `0' `0' `0' `1' `0' `0' `0' `0' `0' `1' `1' `1' `1' `0' `0' `0' `1' `1' `1' `1' `0' `0' `1' `0' `0' `0' Bit 5 Bit 4 Bit 3 Hi-Z Hi-Z `0' `0' `0' `0' `1' `0' `0' `0' `0' `0' `1' `0' `0' `0' `1' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `1' `0' `0' `0' `0' `0' `1' `0' Bit 2 Bit 1 RB VOL VOL Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Note: 1. For Program operations during Erase Suspend Bit 6 is `1', otherwise Bit 6 is `0'.
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M58LW128A, M58LW128B
MAXIMUM RATING Stressing the device above the ratings listed in Table 13, Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 13. Absolute Maximum Ratings
Value Symbol TBIAS TSTG TLEAD VIO VDD, VDDQ VHH Parameter Min Temperature Under Bias Storage Temperature Maximum TLEAD Temperature during soldering Input or Output Voltage Supply Voltage RP Hardware Block Unprotect Voltage -0.6 -0.6 -0.6 -40 -55 Max 125 150 t.b.a. VDDQ +0.6 5.0 10 (1) C C C V V V Unit
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Cumulative time at a high voltage level of 10V should not exceed 80 hours on RP pin.
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M58LW128A, M58LW128B
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measure-
ment Conditions summarized in Table 14, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 14. Operating and AC Measurement Conditions
M58LW128 Parameter Min Supply Voltage (VDD) M58LW128 Input/Output Supply Voltage (VDDQ) Grade 1 Ambient Temperature (TA) Grade 6 Load Capacitance (CL) Clock Rise and Fall Times Input Rise and Fall Times Input Pulses Voltages Input and Output Timing Ref. Voltages 0 to VDDQ 0.5 VDDQ -40 30 3 4 85 C pF ns ns V V 2.7 1.8 0 Max 3.6 VDD 70 V V C Units
Figure 10. AC Measurement Input Output Waveform
Figure 11. AC Measurement Load Circuit
1.3V
1N914 VDDQ VDD VDDQ 0.5 VDDQ 0V
AI00610
3.3k DEVICE UNDER TEST CL 0.1F 0.1F CL includes JIG capacitance
AI03459
DQS
Table 15. Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Typ 6 8 Max 8 12 Unit pF pF
Note: 1. TA = 25C, f = 1 MHz 2. Sampled only, not 100% tested.
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M58LW128A, M58LW128B
Table 16. DC Characteristics
Symbol ILI ILO IDD IDDB IDD1 IDD2 IDD3 IDD4 VIL VIH VOL VOH VHH (1) IHH VLKO Parameter Input Leakage Current Output Leakage Current Supply Current (Random Read) Supply Current (Burst Read) Supply Current (Standby) Supply Current (Reset/Power-Down) Supply Current (Program or Erase, Set Protect Bit, Erase Protect Bit) Supply Current (Erase/Program Suspend) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage RP Hardware Block Unprotect Voltage RP Hardware Block Unprotect Current VDD Supply Voltage (Erase and Program lockout) IOL = 100A IOH = -100A Block Erase in progress, Write to Buffer and Program RP = VHH VDDQ -0.1 8.5 9.5 1 2.2 Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH, fadd = 6MHz E = VIL, G = VIH, fclock = 50MHz E = VIH, RP = VIH RP = VIL Program or Erase operation in progress E = VIH -0.5 VDDQ -0.8 Min Max 1 5 30 50 120 120 50 50 0.8 VDDQ + 0.5 0.1 Unit A A mA mA A A mA mA V V V V V A V
Note: 1. Biasing RP pin to VHH is allowed for a maximum cumulative period of 80 hours.
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M58LW128A, M58LW128B
Figure 12. Asynchronous Bus Read AC Waveforms
tAVAV A1-A23 tELQV tELQX E tGLQV tGLQX G tAVQV tGHQZ tGHQX OUTPUT tEHQZ tEHQX VALID tAXQX
DQ0-DQx
AI06131
Note: Asynchronous Read (M15 = 1), Random Read (M3 = 0)
Table 17. Asynchronous Bus Read AC Characteristics.
M58LW128 Symbol tAVAV tAVQV tELQX tELQV tGLQX tGLQV tEHQX tGHQX tAXQX tEHQZ tGHQZ Parameter Address Valid to Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Output Enable High to Output Transition Address Transition to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Test Condition 150 E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL G = VIL E = VIL Min Max Min Max Min Max Min Min Min Max Max 150 150 0 150 0 30 0 0 0 10 10 ns ns ns ns ns ns ns ns ns ns ns Unit
35/65
M58LW128A, M58LW128B
Figure 13. Asynchronous Latch Controlled Bus Read AC Waveforms
A1-A23 tAVLH tAVLL L tLHLL
VALID tLHAX
tLLLH tELLH tELLL
tEHLX
E tGLQV tGLQX G tLLQX tLLQV DQ0-DQx OUTPUT tGHQZ tGHQX tEHQZ tEHQX
AI06132b
Note: Asynchronous Read (M15 = 1), Latch Enable Controlled (M3 = 1)
Table 18. Asynchronous Latch Controlled Bus Read AC Characteristics
M58LW128 Symbol tAVLL tAVLH tLHLL tLLLH tELLL tELLH tLLQX tLLQV tLHAX tGLQX tGLQV tEHLX Parameter Address Valid to Latch Enable Low Address Valid to Latch Enable High Latch Enable High to Latch Enable Low Latch Enable Low to Latch Enable High Chip Enable Low to Latch Enable Low Chip Enable Low to Latch Enable High Latch Enable Low to Output Transition Latch Enable Low to Output Valid Latch Enable High to Address Transition Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Latch Enable Transition E = VIL, G = VIL E = VIL, G = VIL E = VIL E = VIL E = VIL E = VIL Test Condition 150 E = VIL E = VIL Min Min Min Min Min Min Min Min Min Min Max Min 0 10 10 10 0 10 0 150 10 0 20 0 ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: For other timings see Table 17, Asynchronous Bus Read Characteristics.
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M58LW128A, M58LW128B
Figure 14. Asynchronous Page Read AC Waveforms
A1-A2 A3-A23 tAVQV tELQV tELQX E
VALID VALID
VALID
tAXQX
tGLQV tGLQX G
tAVQV1 tAXQX1
tEHQZ tEHQX
tGHQZ tGHQX DQ0-DQx OUTPUT OUTPUT
AI06133
Note: Asynchronous Read (M15 = 1), Random (M3 = 0)
Table 19. Asynchronous Page Read AC Characteristics
M58LW128 Symbol tAXQX1 tAVQV1 Parameter Address Transition to Output Transition Address Valid to Output Valid Test Condition 150 E = VIL, G = VIL E = VIL, G = VIL Min Max 6 25 ns ns Unit
Note: For other timings see Table 17, Asynchronous Bus Read Characteristics.
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M58LW128A, M58LW128B
Figure 15. Asynchronous Write AC Waveform, Write Enable Controlled
A1-A23 tAVWH E L VALID tWHAX
tELWL G tGHWL W
tWHEH
tWLWH
tWHWL
tWHGL
tDVWH DQ0-DQ15 INPUT tWHDX RB tVPHWH VPP
AI06134
tWHBL
Figure 16. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled
A1-A23 tAVWH tAVLH L tELLL tLLLH tWLLH tLHWH E tELWL G tGHWL W tDVWH DQ0-DQ15 INPUT tWHDX RB tVPHWH VPP
AI06135
VALID
tLHAX tWHAX tLHGL
tWHEH
tWLWH
tWHWL
tWHGL
tWHBL
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M58LW128A, M58LW128B
Table 20. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable Controlled.
M58LW128 Symbol tAVLH tAVWH tDVWH tELWL tELLL tLHAX tLHGL tLHWH tLLLH tLLWH tVPHWH tWHAX tWHBL tWHDX tWHEH tGHWL tWHGL tWHWL tWLWH tWLLH Parameter Address Valid to Latch Enable High Address Valid to Write Enable High Data Input Valid to Write Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable High to Write Enable High Latch Enable low to Latch Enable High Latch Enable Low to Write Enable High Program/Erase Enable High to Write Enable High Write Enable High to Address Transition Write Enable High to Ready/Busy low Write Enable High to Input Transition Write Enable High to Chip Enable High Output Enable High to Write Enable Low Write Enable High to Output Enable Low Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Enable Low to Latch Enable High E = VIL E = VIL E = VIL E = VIL E = VIL E = VIL Test Condition 150 Min Min Min Min Min Min Min Min Min Min Min Min Max Min Min Min Min Min Min Min 10 50 50 0 0 3 35 0 10 50 0 10 90 0 0 20 35 30 70 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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M58LW128A, M58LW128B
Figure 17. Asynchronous Write AC Waveforms, Chip Enable Controlled
A1-A23 tAVEH W tWLEL G tGHEL E L
VALID tEHAX
tEHWH
tELEH
tEHEL
tEHGL
tDVEH DQ0-DQ15 INPUT tEHDX RB tVPHEH VPP
AI06136
tEHBL
Figure 18. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled
A1-A23 tAVLH tAVEH L tWLLL tLLLH tELLH W tWLEL G tGHEL E tDVEH DQ0-DQ15 INPUT tEHDX RB tVPHEH VPP
AI06137
VALID tLHAX tEHAX
tLHEH tLHGL
tEHWH
tELEH
tEHEL
tEHGL
tEHBL
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M58LW128A, M58LW128B
Table 21. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable Controlled
M58LW128 Symbol tAVLH tAVEH tDVEH tWLEL tWLLL tLHAX tLHGL tLHEH tLLLH tLLEH tVPHEH tEHAX tEHBL tEHDX tEHWH tGHEL tEHGL tEHEL tELEH tELLH Parameter Address Valid to Latch Enable High Address Valid to Chip Enable High Data Input Valid to Chip Enable High Write Enable Low to Chip Enable Low Write Enable Low to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable High to Chip Enable High Latch Enable low to Latch Enable High Latch Enable Low to Chip Enable High Program/Erase Enable High to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Ready/Busy low Chip Enable High to Input Transition Chip Enable High to Write Enable High Output Enable High to Chip Enable Low Chip Enable High to Output Enable Low Chip Enable High to Chip Enable Low Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High W = VIL W = VIL W = VIL W = VIL W = VIL W = VIL Test Condition 150 Min Min Min Min Min Min Min Min Min Min Min Min Max Min Min Min Min Min Min Min 10 50 50 0 0 3 35 0 10 50 0 10 90 10 0 20 35 30 70 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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1 X+2Y+1 X+2Y+2 2 X-1 X X+Y X+2Y tKHAX tLHAX tEHQZ tEHQX tGLKH tGHQZ tGHQX tBLKH tKHBH tBHKH tKHBL
tKHQV
0
K
tKHLL
Note: Valid Clock Edge = Rising (M6 = 1)
M58LW128A, M58LW128B
A1-A23
VALID
tLLKH
tLLLH
L
Figure 19. Synchronous Burst Read AC Waveform
tAVKH tAVLH tELKH tELLH
E
G
B tKHQX
tQVKH Q1 Q2 Q3
DQ0-DQx
AI06138
M58LW128A, M58LW128B
Figure 20. Synchronous Burst Read - Continuous - Valid Data Ready Output
K
Output (2)
V
V
V
NV tRLKH
NV
V
V
R
(3)
AI06139
Note: 1. Valid Data Ready = Valid Low during valid clock edge (M8 = 0) 2. V= Valid output, NV= Not Valid output. 3. R is an open drain output. Depending on the Valid Data Ready pin capacitance load an external pull up resistor must be chosen according to the system clock period. 4. When the system clock frequency is between 33MHz and 50MHz and the Y latency is set to 2, values of B sampled on odd clock cycles, starting from the first read are not considered.
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M58LW128A, M58LW128B
Table 22. Synchronous Burst Read AC Characteristics
Symb ol tAVKH tAVLH tBHKH tBLKH tELKH tELLH tGLKH tKHAX tKHLL tKHLH tKHQX tLLKH tLLLH tKHQV tQVKH tRLKH tKHBL tKHBH M58LW128 Parameter Address Valid to Active Clock Edge Address Valid to Latch Enable High Test Condition 150 E = VIL E = VIL Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min Min Min Min 10 10 10 10 10 10 20 10 0 0 3 10 10 20 5 5 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Burst Address Advance High to Active Clock Edge E = VIL, G = VIL, L = VIH Burst Address Advance Low to Active Clock Edge Chip Enable Low to Active Clock Edge Chip Enable Low to Latch Enable High Output Enable Low to Valid Clock Edge Valid Clock Edge to Address Transition Valid Clock Edge to Latch Enable Low Valid Clock Edge to Latch Enable High Valid Clock Edge to Output Transition Latch Enable Low to Valid Clock Edge Latch Enable Low to Latch Enable High Valid Clock Edge to Output Valid Output Valid to Active Clock Edge Valid Data Ready Low to Valid Clock Edge Active Clock Edge to Burst Address Advance Low E = VIL, G = VIL, L = VIH E = VIL E = VIL E = VIL, L = VIH E = VIL E = VIL E = VIL E = VIL, G = VIL, L = VIH E = VIL E = VIL E = VIL, G = VIL, L = VIH E = VIL, G = VIL, L = VIH E = VIL, G = VIL, L = VIH E = VIL, G = VIL, L = VIH
Active Clock Edge to Burst Address Advance High E = VIL, G = VIL, L = VIH
Note: For other timings see Table 17, Asynchronous Bus Read Characteristics.
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M58LW128A, M58LW128B
Figure 21. Reset, Power-Down and Power-Up AC Waveform
W
E, G
DQ0-DQ15 tPHQV tRHWL tRHEL tRHGL
RB tPLRH RP tVDHPH VDD, VDDQ Power-Up and Reset Reset during Program or Erase
AI06140
tPLPH
Note: Write Enable (W) and Output Enable (G) cannot be low together.
Table 23. Reset, Power-Down and Power-Up AC Characteristics
M58LW128 Symbol tPHQV tRHWL tRHEL tRHGL tPLPH tPLRH tVDHPH Parameter 150 Reset/Power-Down High to Data Valid Ready/Busy High to Write Enable Low, Chip Enable Low, Output Enable Low (Program/Erase Controller Active) Reset/Power-Down Low to Reset/Power-Down High Reset/Power-Down Low to Ready High Supply Voltages High to Reset/Power-Down High Min Min Min Max Min 150 10 100 30 0 ns s ns s s Unit
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M58LW128A, M58LW128B
PACKAGE MECHANICAL Figure 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Note: Drawing is not to scale.
Table 24. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 13.90 - 0.50 0 56 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 14.10 - 0.70 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.7795 0.7205 0.5472 - 0.0197 0 56 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 0.5551 - 0.0276 5 inches
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M58LW128A, M58LW128B
Figure 23. TBGA64 - 10x13mm - 8 x 8 ball array, 1mm pitch, Package Outline
D FD FE D1 SD
E
E1
SE
ddd BALL "A1"
A
e
b A1
A2
BGA-Z23
Note: Drawing is not to scale.
Table 25. TBGA64 - 10x13mm - 8 x 8 ball array, 1 mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE 1.000 13.000 7.000 1.500 3.000 0.500 0.500 - 12.900 - - - - - 10.000 7.000 0.400 9.900 - 0.300 0.200 Min Max 1.200 0.350 0.850 0.500 10.100 - 0.100 - 13.100 - - - - - 0.0394 0.5118 0.2756 0.0591 0.1181 0.0197 0.0197 - 0.5079 - - - - - 0.3937 0.2756 0.0157 0.3898 - 0.0118 0.0079 Typ Min Max 0.0472 0.0138 0.0335 0.0197 0.3976 - 0.0039 - 0.5157 - - - - - inches
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M58LW128A, M58LW128B
Figure 24. TBGA80 - 10x13mm - 8 x 10 ball array, 1mm pitch, Package Outline
D FD FE SD D1
SE E E1 BALL "A1" ddd
e
e A
b A2 A1
BGA-Z27
Note: Drawing is not to scale.
Table 26. TBGA80 - 10x13mm - 8 x 10 ball array, 1mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 13.000 9.000 1.000 1.500 2.000 0.500 0.500 12.900 - - - - - - 10.000 7.000 0.400 9.900 - 0.300 0.200 Min Max 1.200 0.350 0.850 0.500 10.100 - 0.100 13.100 - - - - - - 0.5118 0.3543 0.0394 0.0591 0.0787 0.0197 0.0197 0.5079 - - - - - - 0.3937 0.2756 0.0157 0.3898 - 0.0118 0.0079 Typ Min Max 0.0472 0.0138 0.0335 0.0197 0.3976 - 0.0039 0.5157 - - - - - - inches
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M58LW128A, M58LW128B
PART NUMBERING Table 27. Ordering Information Scheme
Example: Device Type M58 Architecture L = Multi-Bit Cell, Burst Mode, Page Mode Operating Voltage W = VDD = 2.7V to 3.6V; VDDQ = 1.8 to VDD Device Function 128A = 128 Mbit (x16), Uniform Block 128B = 128 Mbit (x16/x32), Uniform Block Speed 150 = 150 ns Package N = TSOP56: 14 x 20 mm (M58LW128A) ZA = TBGA64: 10x13mm, 1mm pitch (M58LW128A) ZA = TBGA80: 10x13mm, 1mm pitch (M58LW128B) Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option T = Tape & Reel Packing E = Lead-free Package, Standard Packing F = Lead-free Package, Tape & Reel Packing M58LW128A 150 N 1 T
Note: Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M58LW128A, M58LW128B
APPENDIX A. BLOCK ADDRESS TABLE Table 28. Block Addresses
Block Number 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 Address Range (x16 Bus Width) 7F0000h-7FFFFFh 7E0000h-7EFFFFh 7D0000h-7DFFFFh 7C0000h-7CFFFFh 7B0000h-7BFFFFh 7A0000h-7AFFFFh 790000h-79FFFFh 780000h-78FFFFh 770000h-77FFFFh 760000h-76FFFFh 750000h-75FFFFh 740000h-74FFFFh 730000h-73FFFFh 720000h-72FFFFh 710000h-71FFFFh 700000h-70FFFFh 6F0000h-6FFFFFh 6E0000h-6EFFFFh 6D0000h-6DFFFFh 6C0000h-6CFFFFh 6B0000h-6BFFFFh 6A0000h-6AFFFFh 690000h-69FFFFh 680000h-68FFFFh 670000h-67FFFFh 660000h-66FFFFh 650000h-65FFFFh 640000h-64FFFFh 630000h-63FFFFh 620000h-62FFFFh 610000h-61FFFFh 600000h-60FFFFh 5F0000h-5FFFFFh Address Range (x32 Bus Width) 3F8000h-3FFFFFh 3F0000h-3F7FFFh 3E8000h-3EFFFFh 3E0000h-3E7FFFh 3D8000h-3DFFFFh 3D0000h-3D7FFFh 3C8000h-3CFFFFh 3C0000h-3C7FFFh 3B8000h-3BFFFFh 3B0000h-3B7FFFh 3A8000h-3AFFFFh 3A0000h-3A7FFFh 398000h-39FFFFh 390000h-397FFFh 388000h-38FFFFh 380000h-387FFFh 378000h-37FFFFh 370000h-377FFFh 368000h-36FFFFh 360000h-367FFFh 358000h-35FFFFh 350000h-357FFFh 348000h-34FFFFh 340000h-347FFFh 338000h-33FFFFh 330000h-337FFFh 328000h-32FFFFh 320000h-327FFFh 318000h-31FFFFh 310000h-317FFFh 308000h-30FFFFh 300000h-307FFFh 2F8000h-2FFFFFh Block Number 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 Address Range (x16 Bus Width) 5E0000h-5EFFFFh 5D0000h-5DFFFFh 5C0000h-5CFFFFh 5B0000h-5BFFFFh 5A0000h-5AFFFFh 590000h-59FFFFh 580000h-58FFFFh 570000h-57FFFFh 560000h-56FFFFh 550000h-55FFFFh 540000h-54FFFFh 530000h-53FFFFh 520000h-52FFFFh 510000h-51FFFFh 500000h-50FFFFh 4F0000h-4FFFFFh 4E0000h-4EFFFFh 4D0000h-4DFFFFh 4C0000h-4CFFFFh 4B0000h-4BFFFFh 4A0000h-4AFFFFh 490000h-49FFFFh 480000h-48FFFFh 470000h-47FFFFh 460000h-46FFFFh 450000h-45FFFFh 440000h-44FFFFh 430000h-43FFFFh 420000h-42FFFFh 410000h-41FFFFh 400000h-40FFFFh 3F0000h-3FFFFFh 3E0000h-3EFFFFh 3D0000h-3DFFFFh Address Range (x32 Bus Width) 2F0000h-2F7FFFh 2E8000h-2EFFFFh 2E0000h-2E7FFFh 2D8000h-2DFFFFh 2D0000h-2D7FFFh 2C8000h-2CFFFFh 2C0000h-2C7FFFh 2B8000h-2BFFFFh 2B0000h-2B7FFFh 2A8000h-2AFFFFh 2A0000h-2A7FFFh 298000h-29FFFFh 290000h-297FFFh 288000h-28FFFFh 280000h-287FFFh 278000h-27FFFFh 270000h-277FFFh 268000h-26FFFFh 260000h-267FFFh 258000h-25FFFFh 250000h-257FFFh 248000h-24FFFFh 240000h-247FFFh 238000h-23FFFFh 230000h-237FFFh 228000h-22FFFFh 220000h-227FFFh 218000h-21FFFFh 210000h-217FFFh 208000h-20FFFFh 200000h-207FFFh 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh
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M58LW128A, M58LW128B
Block Number 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 Address Range (x16 Bus Width) 3C0000h-3CFFFFh 3B0000h-3BFFFFh 3A0000h-3AFFFFh 390000h-39FFFFh 380000h-38FFFFh 370000h-37FFFFh 360000h-36FFFFh 350000h-35FFFFh 340000h-34FFFFh 330000h-33FFFFh 320000h-32FFFFh 310000h-31FFFFh 300000h-30FFFFh 2F0000h-2FFFFFh 2E0000h-2EFFFFh 2D0000h-2DFFFFh 2C0000h-2CFFFFh 2B0000h-2BFFFFh 2A0000h-2AFFFFh 290000h-29FFFFh 280000h-28FFFFh 270000h-27FFFFh 260000h-26FFFFh 250000h-25FFFFh 240000h-24FFFFh 230000h-23FFFFh 220000h-22FFFFh 210000h-21FFFFh 200000h-20FFFFh 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh Address Range (x32 Bus Width) 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh Block Number 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Address Range (x16 Bus Width) 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 000000h-00FFFFh Address Range (x32 Bus Width) 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh
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M58LW128A, M58LW128B
APPENDIX B. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 29, 30,
31, 32, 33 and 34 show the addresses used to retrieve the data. When the M58LW128B is used in x16 mode, A1 is the Least Significant Address. Toggling A1 will not change the CFI information available on the DQ15-DQ0 outputs. To read the CFI, in the M58LW128A and M58LW128B devices, in x16 mode, addresses A23-A1 are used; for the x32 mode of the M58LW128B device only addresses A23-A2 are used. To read the CFI, in the M58LW128B device, in x16 mode, the address offsets shown must be multiplied by two in hexadecimal.
Table 29. Query Structure Overview
Offset 00h 01h 10h 1Bh 27h P(h)(1) A(h)(2) (SBA+02)h CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query Table Alternate Algorithm-specific Extended Query Table Block Status Register Sub-section Name Description Manufacturer Code Device Code Command set ID and algorithm data offset Device timing and voltage information Flash memory layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Block-related Information
Note: 1. Offset 0015h (x16) or 00000015h (x32) defines P which points to the Primary Algorithm Extended Query Address Table. 2. Offset 0019h (x16) or 00000019h (x32) defines A which points to the Alternate Algorithm Extended Query Address Table. 3. SBA is the Start Base Address for each block.
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M58LW128A, M58LW128B
Table 30. CFI - Query Address and Data Output
Address (4) A23-A1 (M58LW128A) A23-A2 (M58LW128B) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah(5)
Note: 1. 2. 3. 4. 5. 6.
Data DQ31-DQ16(6) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Instruction DQ15-DQ0 0051h 0052h 0059h 0001h 0000h 0031h 0000h 0000h 0000h 0000h Alternate Algorithm Extended Query address Table 0000h Query ASCII String 0051h; "Q" 0052h; "R" 0059h; "Y"
Primary Vendor: Command Set and Control Interface ID Code Primary algorithm extended Query Address Table: P(h) Alternate Vendor: Command Set and Control Interface ID Code
The x8 or Byte Address mode is not available. With the x16 Bus Width, the value of the address location of the CFI Query is independent of A1 pad (M58LW128B). Query Data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'. For M58LW128B, A1 = Don't Care. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table. DQ31-DQ16 are available in the M58LW128B only. They are in the high-impedance state when the device operates In x16 mode.
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M58LW128A, M58LW128B
Table 31. CFI - Device Voltage and Timing Specification
Address (4) A23-A1 (M58LW128A) A23-A2 (M58LW128B) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
Note: 1. 2. 3. 4. 5.
DQ31-DQ16(5) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
DQ15-DQ0 0027h (1) 0036h (1) 0000h (2) 0000h (2) 0000h (3) 0008h 000Ah 0000h (3) 0000h (3) 0004h 0004h 0000h (3) VDD Min, 2.7V VDD max, 3.6V VPP min - Not Available
Description
VPP max - Not Available 2n s typical time-out for Word Program - Not Available, DWord Program - Not Available 2n s typical time-out for max Buffer Write 2n ms, typical time-out for Erase Block 2n ms, typical time-out for Chip Erase - Not Available 2n x typical for Word Program time-out max - (Word and Dword Not Available) 2n x typical for Buffer Write time-out max 2n x typical for individual Block Erase time-out maximum 2n x typical for Chip Erase max time-out - Not Available
Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV. Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV. Not supported. For M58LW128B, A1 = Don't Care. DQ31-DQ16 are available in the M58LW128B only. They are in the high-impedance state when the device operates In x16 mode.
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M58LW128A, M58LW128B
Table 32. Device Geometry Definition
Address (1) A23-A1 (M58LW128A) A23-A2 (M58LW128B) 27h 28h 0000 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 0000 0000 0000 0000 0000 0000 0000 0000 0004h Device Interface M58LW128B 0000h 0005h 0000h 0001h 007Fh Number (n-1) of Erase Blocks of identical size; n=128 0000h 0000h 0002h Erase Block Region Information x 256 bytes per Erase block (128K bytes) Maximum number of bytes in Write Buffer, 2n Bit7-0 = number of Erase Block Regions in device DQ31-DQ16(2) 0000 N/A DQ15-DQ0 0018h 0001h Description 2n number of bytes memory Size Device Interface M58LW128A
Note: 1. For M58LW128B, A1 = Don't Care. N/A = Not Applicable. 2. DQ31-DQ16 are available in the M58LW128B only. They are in the high-impedance state when the device operates In x16 mode.
Table 33. Block Status Register
Address A23-A1 (M58LW128A) A23-A2 (M58LW128B) bit0 1 bit7-1
Note: 1. BA specifies the block address location, A23-A17.
Data 0
Selected Block Information Block Unprotected Block Protected Reserved for future features
(BA+2)h(1)
0
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M58LW128A, M58LW128B
Table 34. Extended Query information
Address Address A23-A1 (M58LW128A) DQ31-DQ16(1) DQ15-DQ0 offset A23-A2 (M58LW128B) (P)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h 31h 32h 33h 34h 35h 36h 37h 38h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0050h 0052h 0049h 0031h 0031h 008Eh 0001h 0000h Major version number Minor version number Optional Feature: (1=yes, 0=no) bit0, Chip Erase Supported (0=no) bit1, Suspend Erase Supported (1=yes) bit2, Suspend Program Supported (1=yes) bit3, Protect/Unprotect Supported (1=yes) bit4, Queue Erase Supported (0=no) bit5, Instant individual block locking Supported (0=no) bit6, Protection Bits Supported (0=no) bit7, Page Read Supported (1=yes) bit8, Synchronous Read Supported (1=yes) Bit 31-9 reserved for future use Supported functions after Suspend: Program allowed after Erase Suspend (1=yes) (refer to Commands for other allowed functions) Bit 7-1 reserved for future use Block Status Register bit 0 Block Protect Bit Status active (1=yes) bits 1-15 are reserved VDD OPTIMUM Program/Erase voltage conditions VPP OPTIMUM Program/Erase voltage conditions OTP protection: 00 NA, 01 128-bit, 02 OTP area Page Read: 2n Bytes (n = bits 0-7) Synchronous mode configuration fields n where 2n+1 is the number of Words/Double-Words for the burst Length (= 2) n where 2n+1 is the number of Words/Double-Words for the burst Length (= 4) n where 2n+1 is the number of Words/Double-Words for the burst Length (= 8) (x16 mode only) burst continuous Query ASCII string - Extended Table Description
0050h; "P" 0052h; "R" 0049h; "I"
(P+8)h
39h
0000h
0000h
(P+9)h
3Ah
0000h
0001h
(P+A)h (P+B)h (P+C)h (P+D)h (P+E)h (P+F)h (P+10)h (P+11)h (P+12)h (P+13)h (P+14)h
3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h
0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
0001h 0000h 0033h 0033h 0002h 0004h 0004h 0000h 0001h 0002h 0007h
Note: 1. DQ31-DQ16 are available in the M58LW128B only. They are in the high-impedance state when the device operates In x16 mode.
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M58LW128A, M58LW128B
APPENDIX C. FLOW CHARTS Figure 25. Write to Buffer and Program Flowchart and Pseudo Code
Start
Write to Buffer E8h Command, Block Address
Note 1: N+1 is number of Words or Double Words to be programmed
Write N(1), Block Address
Write Buffer Data, Start Address
X=0
X=N NO Note 2: Next Program Address must have same A5-A22.
YES
Write Next Buffer Data, Next Program Address(2)
X=X+1
Program Buffer to Flash Confirm D0h
Read Status Register
b7 = 1 YES Note 3: A full Status Register Check must be done to check the program operation's success. Full Status Register Check(3)
NO
End
AI03635
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M58LW128A, M58LW128B
Figure 26. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend Command: - write B0h - write 70h do: - read status register
Read Status Register
b7 = 1 YES b2 = 1 YES Write FFh
NO
while b7 = 1
NO
Program Complete
If b2 = 0, Program completed
Read Memory Array instruction: - write FFh - one or more data reads from other blocks
Read data from another block
Write D0h
Write FFh
Program Continues
Read Data
Program Erase Resume Command: - write D0h to resume erasure - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase Suspend command was not issued).
AI00612
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M58LW128A, M58LW128B
Figure 27. Erase Flowchart and Pseudo Code
Start
Write 20h
Write D0h to Block Address
Erase command: - write 20h - write D0h to Block Address (A12-A17) (memory enters read Status Register after the Erase command)
Read Status Register
NO Suspend
YES
do: - read status register - if Program/Erase Suspend command given execute suspend erase loop
b7 = 1
NO
Suspend Loop
while b7 = 1
YES b3 = 0 YES b4, b5 = 1,1 NO b1 = 0 YES b5 = 0 YES End
AI00613C
NO
VPP Invalid Error (1)
If b3 = 1, VPP invalid error: - error handler
YES
Command Sequence Error
If b4, b5 = 1,1 Command Sequence error: - error handler
NO
Erase to Protected Block Error
If b1 = 1, Erase to Protected Block Error: - error handler
NO
Erase Error (1)
If b5 = 1, Erase error: - error handler
Note: 1. If an error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase operations.
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M58LW128A, M58LW128B
Figure 28. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend Command: - write B0h - write 70h do: - read status register
Read Status Register
b7 = 1 YES b6 = 1 YES Write FFh
NO
while b7 = 1
NO
Erase Complete
If b6 = 0, Erase completed
Read Memory Array command: - write FFh - one o more data reads from other blocks
Read data from another block or Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command: - write D0h to resume the Erase operation - if the Program operation completed then this is not necessary. The device returns to Read mode as normal (as if the Program/Erase suspend was not issued).
AI00615
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M58LW128A, M58LW128B
Figure 29. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR COMMAND WRITE
90h YES READ SIGNATURE
NO
98h YES CFI QUERY
NO
70h YES READ STATUS
NO
50h YES CLEAR STATUS
NO
READ ARRAY
E8h YES PROGRAM BUFFER LOAD
NO
20h(1) YES ERASE SET-UP
NO
FFh YES
NO
NO
D0h YES C A NO
PROGRAM COMMAND ERROR
D0h YES
ERASE COMMAND ERROR
B Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.
AI03618
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M58LW128A, M58LW128B
Figure 30. Command Interface and Program Erase Controller Flowchart (b)
B A
ERASE
(READ STATUS)
READ STATUS
YES
Program/Erase Controller READY Status bit in the Status Register ? NO
READ ARRAY YES FFh NO
B0h YES
NO
READ STATUS ERASE SUSPEND
NO ERASE SUSPENDED YES
READY ? NO
WAIT FOR COMMAND WRITE
YES
READ STATUS
READ STATUS
YES
70h NO
READ SIGNATURE
YES
90h NO
CFI QUERY
YES
98h NO
PROGRAM BUFFER LOAD
YES
E8h
NO PROGRAM COMMAND ERROR NO D0h D0h NO READ ARRAY
AI03619
YES
READ STATUS
(ERASE RESUME)
YES c
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M58LW128A, M58LW128B
Figure 31. Command Interface and Program Erase Controller Flowchart (c)
B C
PROGRAM
(READ STATUS)
READ STATUS READ ARRAY
YES
READY ? NO
Program/Erase Controller Status bit in the Status Register
B0h YES NO FFh PROGRAM SUSPEND NO PROGRAM SUSPENDED YES YES
NO
READ STATUS
READY ? NO
WAIT FOR COMMAND WRITE
YES
READ STATUS
READ STATUS
YES
70h NO
READ SIGNATURE
YES
90h NO
CFI QUERY
YES
98h NO
READ ARRAY
NO
D0h
YES
READ STATUS
(PROGRAM RESUME)
AI00618
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M58LW128A, M58LW128B
REVISION HISTORY Table 35. Document Revision History
Date 07-Dec-2001 Version -01 First Issue. Version number format modified (major.minor), Revision History moved to end of document. M58LW128A and M58LW128B device codes changed; Manufacturer code clarified. Table 10, Read Electronic Signature, clarified. Data Retention information added to Table 11, Program, Erase Times and Program Erase Endurance Cycles. CFI information (Table 30, Table 31, Table 32 and Table 34) clarified. Document Status changed to Preliminary Data. OTP size corrected. Word program not supported clarified in Table 31, CFI - Device Voltage and Timing Specification and DQ15-DQ0 values changed to 0000h for addresses 1Fh and 23h. Number (n-1) of Erase Blocks of identical size corrected in Table 32, Device Geometry Definition. ASCII for 0049h corrected in Table 34, Extended Query information. E and F lead-free packing options added to Table 27, Ordering Information Scheme. Revision Details
16-Dec-2002
1.1
25-Feb-2003
1.2
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M58LW128A, M58LW128B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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